The electrical behavior of neurons can be more complex in the presence of autapse. In the presence of an autaptic connection, the Izhikevich neuron model can show a variety of dynamic behaviors, such as chaotic behavior. This paper presents a novel, high speed and robust pseudo random number generator based on the autaptic Izhikevich neuron oscillator and its FPGA Implementation. The autaptic Izhikevich neuron model is simulated and dynamically analyzed. Then, the proposed pseudo-random number generator is modeled and simulated using the Xilinx system generator platform, synthesized using Xilinx Synthesis Tool, and implemented on the XILINX SPARTAN-6 XC6SLX9 FPGA evaluation board. As a post processing operation, the XOR function is used to increase the randomness of the output bit sequences. The FPGA Implementation results show that the Implementation cost of the proposed pseudo-random number generator is lower than similar works, and the proposed generator achieves a maximum frequency of 63.2 MHz. The NIST test suite is used for testing the quality of the generated bit sequences. The NIST test results indicates the high quality of the generated random bit sequence.

Adaptive filters are one of the most important building blocks of digital signal processing (DSP) systems which are used in a wide variety of applications such as echo and noise cancellation, channel equalizers, radar and sonar systems. Compared to software Implementation, hardware Implementation of DSP systems has some inherent advantages including higher speed and throughput, integratability and parallel processing. In recent years, Field Programmable Gate Arrays (FPGAs) have received a lot of attention due to their architecture flexibility, low cost and providing the possibility of parallel processing of DSP algorithms. Efficient realization of adaptive filters on FPGAs has always been a motivational and challenging research topic. In this article, we have presented an efficient hardware Implementation of a 9-tap LMS adaptive filter that is much faster and consumes fewer resources compared to similar published works. The results have been verified by comparing those obtained from hardware Implementation of an LMS adaptive noise canceller filter with the results obtained from simulation of a similar filter. Since the permanent collection and processing of meaningful signals are of the fundamentals of management cycle and crisis prevention, the presented design can be well used in hardware equipment related to this area.

The adoption of post-quantum encryption algorithms to replace older asymmetric algorithms is of paramount importance. Diverse categories of post-quantum encryption, including lattice-based and code-based cryptography, are currently in the final stages of NIST's standardization competition, with the aim of providing security against quantum computers. Among the lattice-based key encapsulation mechanisms (KEM) garnering attention in this competition, the NTRU Prime algorithm stands out. The primary challenge in implementing such algorithms revolves around executing resource-intensive polynomial multiplications within a ring structure. Leveraging the Number Theoretic Transform (NTT) allows us to achieve polynomial multiplication with near-linear efficiency (O (n log n)). To enhance hardware efficiency, butterfly structures are frequently employed in NTT multipliers. Our research centers on comparing our approach with the best multiplication Implementations utilized in NTRU Prime on FPGA up to the present version. This involves the redesign and modification of data preprocessing methods and storage structures, resulting in an increase in frequency and a reduction in the utilization of LUT resources.

One of the challenges in the hardware security is withstanding cloning and hardware duplication. In fact this attack aims hardware originality so the defense mechanism should be different from common system security and algorithm protection. Applying Physically Unclonable Functions (PUFs) is one of the most effective protection methods. Physically Unclonable Functions (PUFs) are functions that generate a set of random responses when stimulated by a set of pre-defined requests or challenges. Since these challenge-response schemes extract hidden parameters of complex physical unpredictable properties of substrate materials, such as delay of interconnections and wiring in the CMOS process and devices, they are called physically unclonable functions. They are mainly used for electronic security purposes such as hardware verification and/or device authentication mechanisms, protection of sensitive intellectual property (IP) on devices and protection against insecure hardware connections and communications. PUF-based security mechanisms have some obvious advantages compared to traditional cryptography-based techniques, including more resistance against physical and side channel attacks and suitability for lightweight devices such as RFIDs. In FPGA devices, PUFs are instantiated by exploiting the propagation delay differences of signals caused by manufacturing process variations. However, real Implementation of PUFs on FPGAs is a big challenge given the fact that the resources inside FPGAs are limited, and that it is not easy to simulate the behavior of PUF using existing software tools. In addition, there are a few articles that explain details of the Implementation of PUFs on FPGAs. In practice, it usually takes a long time to get a simple PUF to work both in simulations and on board. In this work, we describe a practical realization of a ring-oscillator based PUF on Xilinx FPGAs and illustrate how such architecture is mapped into some FPGAs from this device family. Using this architecture, we obtain a unique 10-bit code which can be used to identify a chip between many similar devices of the same family in order to provide a reliable access control and authentication mechanism. Simulations are carried out using a dual core computer with 2 GHz clock frequency and 4 GBytes RAM memory.

Masking techniques are used to protect the hardware Implementation of cryptographic algorithms against side-channel attacks. Reconfigurable hardware, such as FPGA, is an ideal target for the secure Implementation of cryptographic algorithms. Due to the restricted resources available to the reconfigurable hardware, efficient secure Implementation is crucial in an FPGA. In this paper, a two-share threshold technique for the Implementation of AES is proposed. In continuation of the work presented by Shahmirzadi et al. at CHES 2021, we employ built-in Block RAMs (BRAMs) to store component functions. Storing several component functions in a single BRAM may jeopardize the security of the Implementation. In this paper, we describe a sophisticated method for storing two separate component functions on a single BRAM to reduce area complexity while retaining security. Out design is well suited for FPGAs, which support both encryption and decryption. Our synthesis results demonstrate that the number of BRAMs used is reduced by 50% without affecting the time or area complexities.